# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog %s -o - | FileCheck %s

--- |
  declare void @llvm.aarch64.settag(i8* nocapture writeonly, i64) argmemonly nounwind writeonly "target-features"="+mte"
  define i32 @stg16_16_16_16_ret() "target-features"="+mte" {
  entry:
    %a = alloca i8, i32 16, align 16
    %b = alloca i8, i32 16, align 16
    %c = alloca i8, i32 16, align 16
    %d = alloca i8, i32 16, align 16
    call void @llvm.aarch64.settag(i8* %a, i64 16)
    call void @llvm.aarch64.settag(i8* %b, i64 16)
    call void @llvm.aarch64.settag(i8* %c, i64 16)
    call void @llvm.aarch64.settag(i8* %d, i64 16)
    ret i32 0
  }

  define void @stg16_store_128() "target-features"="+mte" {
  entry:
    %a = alloca i8, i32 16, align 16
    %b = alloca i8, i32 128, align 16
    call void @llvm.aarch64.settag(i8* %a, i64 16)
    store i8 42, i8* %a
    call void @llvm.aarch64.settag(i8* %b, i64 128)
    ret void
  }

...
---
# A sequence of STG with a register copy in the middle.
# Can be merged into ST2G + ST2G.
# CHECK-LABEL: name:{{.*}}stg16_16_16_16_ret
# CHECK-DAG: ST2Gi $sp, $sp, 2
# CHECK-DAG: ST2Gi $sp, $sp, 0
# CHECK-DAG: $w0 = COPY $wzr
# CHECK-DAG: RET_ReallyLR implicit killed $w0

name:            stg16_16_16_16_ret
tracksRegLiveness: true
stack:
  - { id: 0, name: a, size: 16, alignment: 16 }
  - { id: 1, name: b, size: 16, alignment: 16 }
  - { id: 2, name: c, size: 16, alignment: 16 }
  - { id: 3, name: d, size: 16, alignment: 16 }
body:             |
  bb.0.entry:
    STGi $sp, %stack.0.a, 0 :: (store (s128) into %ir.a)
    STGi $sp, %stack.1.b, 0 :: (store (s128) into %ir.b)
    STGi $sp, %stack.2.c, 0 :: (store (s128) into %ir.c)
    $w0 = COPY $wzr
    STGi $sp, %stack.3.d, 0 :: (store (s128) into %ir.d)
    RET_ReallyLR implicit killed $w0

...

---
# A store in the middle prevents merging.
# CHECK-LABEL: name:{{.*}}stg16_store_128
# CHECK: ST2Gi $sp, $sp, 2
# CHECK: ST2Gi $sp, $sp, 4
# CHECK: ST2Gi $sp, $sp, 6
# CHECK: STGi  $sp, $sp, 8
# CHECK: STRBBui
# CHECK: ST2Gi $sp, $sp, 0
# CHECK: RET_ReallyLR

name:            stg16_store_128
tracksRegLiveness: true
stack:
  - { id: 0, name: a, size: 16, alignment: 16 }
  - { id: 1, name: b, size: 128, alignment: 16 }
body:             |
  bb.0.entry:
    STGi $sp, %stack.0.a, 0 :: (store (s128) into %ir.a)
    renamable $w8 = MOVi32imm 42
    ST2Gi $sp, %stack.1.b, 6 :: (store (s256) into %ir.b + 96, align 16)
    ST2Gi $sp, %stack.1.b, 4 :: (store (s256) into %ir.b + 64, align 16)
    ST2Gi $sp, %stack.1.b, 2 :: (store (s256) into %ir.b + 32, align 16)
    STRBBui killed renamable $w8, %stack.0.a, 0 :: (store (s8) into %ir.a, align 16)
    ST2Gi $sp, %stack.1.b, 0 :: (store (s256) into %ir.b, align 16)
    RET_ReallyLR

...
